at24cm0x 1.0
at24cm0x driver library
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Display Clock Command

Command and options for configuring the SSD130X display clock timing and frequency. More...

Macros

#define SSD130X_CMD_SET_DISPLAY_CLOCK   0xD5
#define SSD130X_CMD_SET_DISPLAY_CLOCK_DIVIDE_RATIO   0x00
#define SSD130X_CMD_SET_DISPLAY_CLOCK_FREQUENCY   0x80

Detailed Description

Command and options for configuring the SSD130X display clock timing and frequency.

The SSD130X_CMD_SET_DISPLAY_CLOCK macro defines the command byte used to configure the display's internal clock.

Note
The options allow adjustment of the clock divide ratio and oscillator frequency, which determine the timing and refresh rate of the SSD130X display.

Possible frequency settings:

  • Oscillator frequency setting bits can range from 0x00 to 0xF0 (higher nibble of the byte).
  • Common base oscillator frequency options include:
    • 0x00: Lowest frequency
    • 0x0F: Highest frequency (see display datasheet for exact mapping)

Possible clock divide ratios:

  • Divide ratio can be set from 0x00 (divide by 1) up to 0x0F (divide by 16)
  • Lower divide ratios result in higher frame rates; higher divide ratios can reduce current consumption at the expense of slower updates.

Macros:

Usage Example: To set the display clock, send the command SSD130X_CMD_SET_DISPLAY_CLOCK followed by the desired divide ratio and frequency setting ()SSD130X_CMD_SET_DISPLAY_CLOCK_DIVIDE_RATIO | SSD130X_CMD_SET_DISPLAY_CLOCK_FREQUENCY).

Macro Definition Documentation

◆ SSD130X_CMD_SET_DISPLAY_CLOCK

#define SSD130X_CMD_SET_DISPLAY_CLOCK   0xD5

◆ SSD130X_CMD_SET_DISPLAY_CLOCK_DIVIDE_RATIO

#define SSD130X_CMD_SET_DISPLAY_CLOCK_DIVIDE_RATIO   0x00

Clock divide ratio setting

◆ SSD130X_CMD_SET_DISPLAY_CLOCK_FREQUENCY

#define SSD130X_CMD_SET_DISPLAY_CLOCK_FREQUENCY   0x80

Oscillator frequency setting